, 32.8khz_{) key interrupt input(quasi-interrupt) falling edge detection(ks0, ks1) stand by mode(idle, stop) release power on reset (program rom mask option) initial power on reset reset operation under 2.0v lcd display 16 segments and 4 common pins 2, 3, and 4 common selectable internal resistor for lcd bias(170 k w ) memory mapped i/o structure data memory bank 15 power-down modes idle: only cpu clock stops stop: main system clock and cpu clock stops subsystem clock stop mode oscillation sources main: internal rc osc(1mhz) sub: external 32.8khz crystal only instruction execution times main system clocks:4, 8, 64 m s at 1mhz subsystem clocks: 122 m s at 32.768 khz operating voltage range 1.8 v to 5.5 v at 1mhz/32.8khz power consumption(the lvd circuit needs 100ua or more current on all the below mode) main: operation - 0.5ma at 1mhz, 3v sub: operation - 12 m a at lcd off, 3v idle - 5 m a at lcd off idle, 3v stop - 1 m a at 5.5v operating temperature - 40 c to 85 c package type 32-sop-450a package
S3C7281 product overview 1- 3 block diagram basic timer program status word arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block instruction register xt in program counter main clock (internal rc osc) stack pointer p1.1/ks1 xt out i/o port 0 output port 2 i/o port 1 p0.3 p0.2/ buz p0.1/buz p0.0/clo p1.0/ks0 p2.4-p2.7/ seg13-seg10 sub clock p2.0-p2.3/ seg17-seg14 64 x 4-bit data memory 1024-byte program memory watchdog timer power on reset lcd driver/ controller watch timer com0-com1 com2-com3/ seg0-seg1 seg2-seg9 seg10-seg17/ p2.7-p2.0 * agp option figure 1-1. S3C7281 simplified block diagram
product overview s3 c7281 1- 4 pin assignments v ss xt in xt out test p1.0/ks0 p1.1/ks1 reset com0 com1 com2/seg0 com3/seg1 seg2 seg3 seg4 seg5 seg6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p0.0/clo p0.1/buz p0.2/ buz p0.3 p2.0/seg17 p2.1/seg16 p2.2/seg15 p2.3/seg14 p2.4/seg13 p2.5/seg12 p2.6/seg11 p2.7/seg10 seg9 seg8 seg7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S3C7281 (32-sop-450a) note: reserved pins for the otp version in the future sclk (note) sdat (note) figure 1-2. S3C7281 32-sop pin assignment diagram
S3C7281 product overview 1- 5 pin descriptions table 1-1. S3C7281 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is pos sible. 1-bit unit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. individual pins can be allocated as input or output(1-bit unit). the n-channel open-drain or push- pull output can be selected by software(1-bit unit). 31 30 29 28 clo buz buz p1.0 p1.1 i/o 4-bit i/o port. 1-bit or 4-bit write and test is pos sible. 4-bit unit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. the pins can be allocated as input or output(4-bit unit). the n-channel open-drain or push-pull output can be selected by software(4-bit unit). 5 6 ks0 ks1 p2.0 - p2.7 o 8-bit output port. 1-bit, 4-bit, 8-bit read/write and test is pos sible. the n-channel open-drain or push-pull output can be selected by software(4-bit unit). 27 - 20 seg17- seg10 clo i/o clock output. 31 p0.0 buz i/o buzzer signal output. 30 p0.1 buz i/o inverted buzzer signal output. 29 p0.2 ks0 ks1 i/o external interrupt with falling edge detection. 5 6 p1.0 p1.1 seg0 seg1 o lcd segment signal output. 10 11 com0 com1 seg2-seg9 o lcd segment signal output. 12 - 19 ? seg10-seg17 o lcd segment signal output. 20 - 27 p2.7 - p2.0 com0 com1 o lcd common signal output. 8 9 ? com2 com3 o lcd common signal output. 10 11 seg0 seg1 xt in xt out ? crystal oscillator pins for subsystem clock. 2 3 ? v dd ? main power supply. 32 ? v ss ? ground. 1 ? reset i chip reset signal input. 7 ? test i chip test signal input (must be connected to v ss ). 4 ?
product overview s3 c7281 1- 6 table 1-1. S3C7281 pin descriptions (continued) pin name pin type share pin circuit type reset value p0.0 - p0.2 p0.3 i/o clo, buz, buz e-2 input p1.0 - p1.1 i/o ks0, ks1 e-2 input p2.0 - p2.7 o seg17 - seg10 h-28 low output com0, com1 o ? h-4 low output com2, com3 o seg0, seg1 h-6 low output seg2 - seg9 o ? h-5 low output seg10 - seg17 o p2.7 - p2.1 h-28 low output v dd ? ? ? ? v ss ? ? ? ? reset i ? b ? xt in , xt out ? ? ? ? test i ? ? ?
S3C7281 product overview 1- 7 pin circuit diagrams schmitt trigger in v dd pull-up resistor figure 1-3. pin circuit type b v dd pne output disable data pull-up resistor enable v dd i/o pull-up resistor p-ch n-ch schmitt trigger figure 1-4. pin circuit type e-2 out com v lc0 v lc1 v ss v lc2 figure 1-5. pin circuit type h-4 out seg v lc0 v lc1 v ss v lc2 figure 1-6. pin circuit type h-5
product overview s3 c7281 1- 8 out seg/com v lc0 v lc1 v ss v lc2 figure 1-7. pin circuit type h-6 output seg v lc0 v lc1 v ss v lc2 p-ch n-ch v dd output disable data pne figure 1-8. pin circuit type h-28
S3C7281 electrical data 13- 1 13 electrical data overview in this section, information on S3C7281 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolut e maximum ratings ? d.c. electrical characteristics ? power-on reset circuit characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? power-on reset timing ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c 7281 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage vi ports 0, 1 ? 0.3 to v dd + 0.3 v output voltage vo ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 15 ma all i/o pins active ? 30 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for pins 0, 1, 2 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 13-2. d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 0, 1, and reset 0.8v dd ? v dd v v ih2 xt in v dd ? 0.1 v dd input low voltage v il1 ports 0, 1, and reset ? ? 0.2v dd v v il2 xt in 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = - 1 ma ports 0, 1, 2 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0, 1, 2 ? ? 2.0 v v dd = 1.8 v to 5.5 v i ol = 1.6 ma 0.4
S3C7281 electrical data 13- 3 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i = v dd xt in 20 input low leakage current i lil1 v i = 0 v all input pins except reset and xt in ? ? ? 3 i lil2 v i = 0 v xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 output low leakage current i lol v o = 0 v all output pins ? ? ? 3 pull-up resistor r l1 v i = 0 v; v dd = 5v ports 0, 1 25 50 75 k w v dd = 3v 50 100 150 r l2 v i = 0 v; v dd = 5v; reset 100 200 300 v dd = 3v 250 500 750 lcd voltage dividing resistor r lcd t a = + 25 c 120 170 220 ? v lc0 - com i ? voltage drop (i = 0-3) v dc ? 15 ua per common pin ? ? 120 mv ? v lc0 - seg x ? voltage drop (x = 0?17) v ds ? 15 ua per common pin ? ? 120 middle output v lc0 v dd = 1.8v to 5.5v, 1/3 bias v dd -0.2 v dd v dd +0.2 v voltage (note) v lc1 lcd clock = 0hz 2v dd /3-0.2 2v dd /3 2v dd /3+0.2 v lc2 v dd /3-0.2 v dd /3 v dd /3+0.2 note: it is middle output voltage when 1/4 duty and 1/3 bias.
electrical data s3c 7281 13- 4 table 13-2. d.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) v dd = 5 v 10% internal rc oscillator 1.15 mhz ? 1.0 2.5 ma disable lvr (5) v dd = 3 v 10% 1 mhz 0.5 1.2 i dd2 (2) idle mode v dd = 5 v 10% internal rc oscillator 1.15 mhz 0.5 1.0 v dd = 3 v 10% 1 mhz 0.15 0.4 i dd3 (3) v dd = 3 v 10% 32 khz crystal oscillator ? 12.0 24 m a i dd4 (3) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5.0 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 2.5 5 stop mode; v dd = 3 v 10% xt in = 0v 0.5 3 v dd = 5 v 10% scmod = 0.2 3 v dd = 3 v 10% 0000b 0.1 2 notes: 1. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents. 2. data includes power consumption for subsystem clock oscillation. 3. when the system clock cont rol register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b". 5. current in the lvr circuit is not included.
S3C7281 electrical data 13- 5 table 13-2. d.c. electrical characteristics (concluded) (t a = - 40 c to + 85 c, v dd = 2.2 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) v dd = 5 v 10% internal rc oscillator 1.15 mhz ? 1.12 2.7 ma enable lvr (5) v dd = 3 v 10% 1 mhz 0.6 1.35 i dd2 (2) idle mode v dd = 5 v 10% internal rc oscillator 1.15 mhz 0.62 1.2 v dd = 3 v 10% 1 mhz 0.25 0.55 i dd3 (3) v dd = 3 v 10% 32 khz crystal oscillator ? 112.0 174 m a i dd4 (3) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 105.0 165 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 122.5 205 stop mode; v dd = 3 v 10% xt in = 0v 100.5 153 v dd = 5 v 10% scmod = 120.2 203 v dd = 3 v 10% 0000b 100.1 152 notes: 1. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents. 2. data includes power consumption for subsystem clock oscillation. 3. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b". 5. when lvr is enabled, the lvr circuit needs 10 0 m a or more current on the all below mode.
electrical data s3c 7281 13- 6 table 13-3. power-on reset circuit characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units power-on reset voltage high v ddh ? 2.2 ? 5.5 v power-on reset voltage low v ddl ? 0 1.8 2.0 v power supply voltage rise time t r ? 10 ? (1) m s power supply voltage off time t off ? 0.5 ? ? s power-on reset circuit i ddpr v dd = 5 v 10% ? 120 200 m a consumption current (2) v dd = 3 v 10% ? 100 150 note: 1. 2**5/fx(= 8.19ms at fx = 1mhz) 2. current consumed when power-on reset circuit is provided internally. table 13-4. sub system clock oscillator characteristics (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillation frequency (1) ? 32 32.768 35 khz oscillator xt in c1 c2 xt out stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5.5 v ? ? 10 external xt in input frequency (1) ? 32 ? 100 khz clock xt in xt out xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs.
S3C7281 electrical data 13- 7 table 13-5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 13-6. a.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 1.8 v to 5.5 v 4 ? 80 m s with subsystem clock (fxt) 114 122 125 interrupt input high, low width f inth , f intl ks0, ks1 10 ? ? reset input low width t rsl input 10 ? ? note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
electrical data s3c 7281 13- 8 250 khz cpu clock 12.5 khz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 15.6 khz 50 khz 1.8 v 5.5 v main osc frequency (internal rc) (divided by 4) 1.0 mhz figure 13-1. standard operating voltage range table 13-7. ram data retention supply voltage in stop mode (t a = - 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to del ay execution of cpu instructions during the wait time.
S3C7281 electrical data 13- 9 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 13-2. stop mode release timing when initiated by reset execution of stop instruction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 13-3. stop mode release timing when initiated by interrupt request 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13-4. a.c. timing measurement points (except for xt in )
electrical data s3c 7281 13- 10 xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 13-5. clock timing measurement at xt in reset t rsl 0.2 v dd figure 13-6. input timing for reset signal
S3C7281 electrical data 13- 11 ks0, ks1 t inth t intl 0.8 v dd 0.2 v dd figure 13-7. input timing for external quais-interrupts t off v dd t off v dd v ddh figure 13-8. power-on reset timing
S3C7281 mechanical data 1 4- 1 14 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram
mechanical data S3C7281 1 4- 2 32-sop-450a 20.30 max 19.90 0 .20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 0.20 0.90 0.20 0.05 min 2.00 0.10 2.20 max 0.10 max 1.27 note : dimensions are in millimeters. 12.00 0 .30 #32 #1 (0.43) 0.40 0.10 figure 14-1. 32-sop package dimensions}